Appendix C. Memory and IO Map
The NES architecture is based on the 8-bit 6502 CPU which can access 64k of memory at any one time. The 6502 processor does not have specific instructions to access external ports, so instead uses dedicated memory locations instead the way to read and write to external devices.
This appendix will show the memory map in more detail and list all the memory mapped ports built into the original hardware.
C.1 Memory Map
The NES’s 64k memory space is split into multiple sections, the lower 4k of memory contains all of the dedicated sections for the CPU and the next section the PPU memory mapped registers. The upper 48k of space is split up into areas that are provided by the game cartridge.
Figure C.1 NES/Famicom Memory Map
The cartridge space from $4020 to $ffff can be used for any purpose, such as ROM, RAM and memory mapped registers. Many common mappers place ROM and save/work RAM in these locations:
$6000-$7fff: Battery-back save or work RAM (commonly referred to as WRAM or PRG-RAM)
$8000-$ffff: ROM and mapper memory mapped registers.
If using DPCM 1-bit digital samples, the samples data needs to be located from $c000 to $fff1.
The CPU expects the interrupt vectors are in a fixed position at the end of the cartridge space.
$fffa-$fffb: NMI vector
$fffc-$fffd: Reset vector
$fffe-$ffff: IRQ/BRK vector
C.2 IO Map
The 6502 does not have any direct port communication instructions, instead memory addresses are allocated as read and write port addresses.