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Big-endian

As explained in Latency

A byte order that stores the most significant byte of a multi-byte value first and the least significant byte last.

Big-endian stores the most significant byte of a multi-byte value first and the least significant byte last. For a 32-bit value, this places the highest-order bits at the lowest memory address. section 7.3

32-bit representation

The value 0xE011CFD0 is stored in big-endian order as the consecutive bytes 0xE0, 0x11, 0xCF, and 0xD0. Little-endian reverses that byte sequence. section 7.3

Big-endian matters when values cross memory, serialization, and network boundaries:

  • CPU architecture determines the in-memory byte order of multi-byte values. section 7.3
  • Many network protocols use big-endian as network byte order, despite little-endian being common on modern ARM and x86 CPUs. section 7.3
  • Serialization and deserialization must transform values accurately between in-memory and external representations. section 7.3
Figure 7.2 Serialization transforms the in-memory representation of data (shown on the left as a Rust struct) to a serialized format such as JSON (shown on the right). Deserialization performs the opposite transformation from a serialized format to an in-memory representation.
Figure 7.4: Serialization transforms in-memory representation to a serialized format such as JSON. Deserialization performs the opposite transformation from serialized format to in-memory representation.

Use the serialization diagram to relate byte-order decisions to transformations between in-memory data and formats such as JSON. section 7.3

How Latency covers it

How deep it goes
Explains byte layouts for 32-bit integers and links them to serialization, but does not provide implementation code.
Examples
Uses 0xE011CFD0 and its byte sequence to contrast big-endian with little-endian representation.
What you can do after
Evaluate byte sequences and recognize when network or serialized data uses big-endian order.
How it connects
Connects big-endian with little-endian, CPU architecture, serialization, deserialization, and network byte order.

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This explainer was generated by Manning's knowledge graph from the text of Latency. The section links point to the parts of the book it draws on.