A cache hit occurs when a requested memory location is found in the cache being checked. CPUs check L1, then L2, then L3, before accessing main memory. section 12.1.2
Sequential slice access
When sum first accesses s[0], the address causes a compulsory cache miss and may load the entire memory block containing elements 0 through 7. Accessing elements 1 through 7 then produces cache hits. Accessing s[8] causes another compulsory miss, while elements 9 through 15 hit the newly loaded block. Iterating over all 16 int64 values therefore produces 2 compulsory misses and 14 cache hits. section 12.1.2
func sum(s []int64) int64 {
var total int64
length := len(s)
for i := 0; i < length; i++ {
total += s[i]
}
return total
}
Use the sequential sum implementation to connect adjacent slice accesses with cache-line reuse. section 12.1.2
