A cache miss occurs when the requested address is absent from a CPU cache. The CPU checks L1, then L2 and L3, before reaching main memory if necessary. Caches copy memory in blocks called cache lines, so one miss can make nearby data available for later accesses. section 12.1.2
The first access pays for nearby elements
Suppose a Go function sums 16 consecutive int64 values, and a cache line holds eight of them. On the first pass, reading s[0] and s[8] causes two compulsory misses: neither block is cached yet. If the CPU caches both blocks, the other 14 reads are hits. A miss on one element does not mean every subsequent element misses. section 12.1.2
Not every miss is a first-access miss. Cache placement can make different memory blocks compete for the same cache set. If one displaces another, reading the displaced block again causes a conflict miss—even though other sets may be available. This makes access stride important, not just the number of values read. section 12.1.5
func calculateSum512(s [][512]int64) int64 { #1
var sum int64
for i := 0; i < len(s); i++ {
for j := 0; j < 8; j++ {
sum += s[i][j]
}
}
return sum
}
func calculateSum513(s [][513]int64) int64 { #2
// Same implementation as calculateSum512
}
Compare the Go matrix traversals: they read the first eight values of each row, but row widths of 512 and 513 int64 values produce different cache behavior. In the described 32 KB, eight-way L1D cache, 64 sets and 64-byte lines make 4 KB a critical stride. Rows 512 elements wide hit that stride and concentrate accesses in one set; 513-element rows avoid it. section 12.1.5
