Compilation lowers high-level model code into machine-level code that better matches target hardware, improving inference speed and potentially reducing cost. A practical pipeline converts PyTorch or TensorFlow models into an intermediate representation such as TorchScript, MLIR, or ONNX, then generates hardware-specific code for GPUs, TPUs, or CPUs. section 6.1.1
The intermediate representation separates framework tooling from hardware-specific compilation:
- Framework developers provide conversion into shared intermediate representations. section 6.1.1
- Hardware vendors provide compilation from those representations to their processors. section 6.1.1
- Existing tools such as llama.cpp and pre-quantized model formats reduce repeated optimization work. section 6.1.1
TensorRT compilation
A TensorRT workflow loads GPT-2 with PyTorch, moves it to CUDA, traces it with TorchScript, and supplies input shapes and tensor types for compilation. Inputs can use static dimensions or bounded dynamic shapes. section 6.1.1
Figure 6.2 An example of an unoptimized network compared to the same network optimized using graph optimization. CBR is a NVIDIA fused layer kernel that simply stands for Convolution, Bias, and ReLU. See the following NVIDIA blog post for reference: https://mng.bz/PNvw.
Graph optimization can replace an unoptimized network with fused operations such as NVIDIA's convolution-bias-ReLU kernel. section 6.1.1






