Coherency wall

As explained in Learn Concurrent Programming with Go

The coherency wall is a scalability limit caused by the increasing complexity, cost, and performance impact of maintaining cache coherence across many processor cores.

The coherency wall is a scalability limit for multiprocessor systems. As processor counts rise, maintaining consistent cached copies of shared memory becomes more complex, costly, and potentially harmful to performance. section 3.1

Cache coherence manages shared data through mechanisms such as:

• Listening for memory-update messages on the bus. section 3.1
• Applying an update to a cached copy or invalidating its cache line. section 3.1
• Fetching an invalidated variable from memory the next time a thread needs it. section 3.1

Figure 3.4 Updating shared variables in an architecture with caches

Shows how cached copies of shared variables are updated or invalidated across processors. section 3.1

How Learn Concurrent Programming with Go covers it

How deep it goes

Defines the limit and outlines cache invalidation, but stops short of detailed protocol or hardware analysis.

Examples

Uses bus update messages and shared-variable cache updates, illustrated by a cache architecture figure.

What it assumes

Assumes memory sharing, caches, and multiprocessor communication as the surrounding concepts.

What you can do after

Evaluate how cache-coherence costs can limit performance as processor counts increase.

How it connects

Ties cache coherence to memory sharing, processor caches, cache lines, and multiprocessor systems.

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