A conflict miss occurs when memory blocks compete for a restricted cache set, causing a miss that partitioning would otherwise avoid. A critical stride repeatedly maps accesses to the same set. section 12.1.5
The 512-column trap
A 32 KB, eight-way L1D cache with 64 sets and 64-byte lines has a 4 KB critical stride. Because 4 KB contains 512 int64 values, calculateSum512 repeatedly creates poor cache distribution; calculateSum513 avoids that critical stride despite identical loop logic. section 12.1.5
