A control hazard is the dependency created when a conditional branch determines which instructions may execute next. Treating those instructions as freely parallel can produce speculative work that must later be discarded. section 12.3
Conditional execution after an increment
In `s[0]++` followed by `if s[0]%2 == 0 { s[1]++ }`, the branch outcome controls the following increment. A processor may predict the condition from recent history and execute both paths speculatively. If the prediction is wrong, it flushes the execution pipeline, causing a stated penalty of 10 to 20 clock cycles. section 12.3
s[0]++
if s[0]%2 == 0 {
s[1]++
}
Inspect the compact increment-and-branch sequence that exposes the control dependency. section 12.3
Distinguish the hazard from nearby instruction-level parallelism concerns:
- Use branch prediction as the processor-level response to control hazards; recognize that incorrect predictions incur pipeline-flush costs. section 12.3
- Do not confuse control hazards with data hazards, where one instruction needs another instruction's result. section 12.3
