Memory barrier
A memory barrier is a synchronization operation that constrains the ordering or visibility of memory accesses across concurrent execution.
Latency
A CPU memory barrier is an instruction or mechanism that constrains hardware-level reordering of memory operations.
- How it is used
- Controls memory-operation ordering where lock-free or wait-free synchronization needs finer control than mutual exclusion.
- How deep it goes
- Defines barrier categories and architecture differences, then works through a publication failure and acquire-release queue operations.
- Examples
- Uses a two-thread completion flag with observed relaxed-ordering failure and a Rust bounded single-producer, single-consumer queue.
- What you can do after
- Build it from scratch: place acquire and release orderings on atomic publication and index operations in the shown queue.
C# Concurrency: Asynchronous and multithreaded programming
A memory barrier is a synchronization operation that prevents reads and writes from being reordered across it.
- How it is used
- Explains how synchronization controls memory-access reordering when threads share data.
- How deep it goes
- Defines acquire, release, and barrier semantics, then stops short of detailed CPU-specific implementation.
- Examples
- Uses a shared counter and initialization assignment to illustrate compiler and memory-access reordering.
- What you can do after
- Evaluate shared-data synchronization and choose locking as the straightforward ordering safeguard.
Read how C# Concurrency: Asynchronous and multithreaded programming explains memory barrier →
C++ Concurrency in Action, Second Edition
A fence is a synchronization operation that constrains the ordering of memory operations without itself accessing the protected object.
- How it is used
- Constrains memory-operation ordering, commonly by pairing fences with relaxed atomic operations.
- How deep it goes
- Explains release/acquire synchronization and ordering non-atomic accesses, but does not provide an exhaustive fence reference.
- Examples
- Uses atomic x and y across two threads, then replaces x with a non-atomic bool to illustrate enforced ordering.
- What you can do after
- Apply release and acquire fences to order relaxed atomic operations or protect ordered accesses to non-atomic data.
Read how C++ Concurrency in Action, Second Edition explains memory barrier →
Related concepts
- synchronizationkind of · Synchronization coordinates operations, events, clocks, data, or states to establish required timing, ordering, visibility, or consistency relationships.
- happens-before relationproduces · A happens-before relation is a partial ordering between events that establishes when one causally precedes another for reasoning about execution and effects.
- atomic operationuses · An atomic operation accesses or updates shared state as an indivisible action with respect to concurrent operations.
- synchronizes-with relationproduces · A synchronizes-with relation is an inter-thread ordering relationship in which a synchronization operation establishes visibility of effects from one thread to another.
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