Memory topology is the organization and connectivity of processors, caches, memory banks, and their interconnects. It determines whether a memory access is uniform, local, or remote, and therefore affects latency-sensitive applications. section 3.4 section 7.4.5
Figure 3.4 UMA and NUMA architectures. The left side of the figure represents a UMA architecture where all CPU cores have the same access latency to DRAM. The right side represents a NUMA architecture with two nodes. CPUs that are in the same node can access NUMA node local memory faster than memory in a remote node.
Compare UMA, where cores reach DRAM with uniform latency, with NUMA, where local memory is faster than memory attached to another node. section 3.4
Use the topology model to reason about latency:
- UMA gives each CPU core the same access latency to main memory, simplifying multicore placement. section 3.4
- NUMA gives each CPU faster access to local memory than to remote memory, so computation and data should be colocated. section 3.4
- Treat cache capacity and access patterns as part of the topology: L1 access can be far faster than DRAM, while repeated full-dataset scans can trash caches. section 7.4.5
NUMA-aware key-value store
Partition the keyspace across NUMA nodes or CPU cores, forward each lookup to a nearby core, and keep its working data on local memory. Discover the machine layout with hwloc or operating-system services, then use Linux mbind() to bind a data structure's memory to selected CPUs. section 3.4 section 7.4.5
