Out-of-order execution lets a CPU run later instructions when their operands and execution resources are available, even while an earlier instruction waits. It must preserve the same architectural state that strictly ordered execution would produce. section 11.4
The technique hides memory latency: while an instruction waits for data from relatively slow main memory, the CPU can execute independent future instructions. Cache access can be up to 100 times faster than main-memory access, making this overlap valuable for throughput. section 11.4
Distinguish the technique from related performance mechanisms:
- Out-of-order execution schedules available work around stalls without changing the program’s visible result. section 11.4
- Speculative execution goes further by predicting a future branch path; successful predictions commit, while failed predictions discard their results. section 11.4
- Its importance reflects hardware optimization trends: transistor growth enabled more parallel execution units, while frequency gains later plateaued. section 1.3.3
