Power-saving optimization uses hardware or operating-system mechanisms to reduce energy consumption by limiting or adapting component activity. In latency-sensitive systems, those mechanisms can introduce latency variance, especially in the tail, because the software does not directly control their behavior. section 2.3.2 section 2.3
Account for power-saving behavior as part of broader hardware and latency tuning:
- Treat CPU frequency scaling and hardware power saving as potential contributors to unpredictable latency. section 2.3.2
- Prioritize awareness and measurement over assumptions, because programmers cannot directly control many hardware-level optimizations. section 2.3.2
- Separate energy or throughput benefits from latency goals: hardware techniques can improve typical efficiency while worsening tail behavior. section 2.3.2
- Consider the surrounding hardware effects, including cache behavior, speculative execution, simultaneous multithreading, and frequency scaling. section 2.3.2
The practical response is to account for power-saving behavior while writing and tuning low-latency code rather than treating software changes as the only source of control. Technology-agnostic latency practices remain possible, but lower-level optimizations depend more strongly on the language, runtime, and framework. section 2.3.2 section 2.3
