A CPU emulator is software that reproduces instruction execution behavior. A minimal emulator models a CPU with registers, an opcode, and an operation that changes register data. section 5.0 section 5.7.1
A small emulator follows this execution sequence:
- Initialize the CPU and its registers. section 5.7.1
- Load values into registers and place an opcode in the current operation. section 5.7.1
- Read and split the opcode into fields identifying the operation and operands. section 5.7.1
- Match the decoded fields to an operation and execute it. section 5.7.1
The Adder
The first CHIP-8 prototype supports one instruction: addition. With 5 in one register, 10 in another, and opcode 0x8014 loaded, it decodes the opcode as an addition using registers 0 and 1, producing 15. section 5.7.1 section 5.7.2
Listing 5.18 Definition of the CPU used in listing 5.22
struct CPU {
current_operation: u16, #1
registers: [u8; 2], #2
}
Inspect the compact CPU definition: one current opcode and two u8 registers provide the state needed for the first operation. section 5.7.1
