A program accesses memory through virtual addresses, not physical addresses in RAM. The memory management unit (MMU) is CPU hardware that translates those addresses. The operating system maintains a page table containing the translation information; the CPU performs the translation when the program accesses memory. section 6.4.1 section 6.4.3
Two details make that translation practical:
- Virtual memory is divided into pages, typically 4 KB each. Mapping blocks avoids storing a separate translation for every variable. section 6.4.3
- The CPU caches recent translations in a translation lookaside buffer (TLB). Without a cached translation, a memory access can require an additional memory lookup. section 6.4.3
Following a memory access
Imagine a program repeatedly accessing data on the same virtual-memory page. The first access may need translation information from memory; later accesses can benefit from a cached translation. This is one reason lean data structures can perform better than deeply nested ones: reaching the TLB’s capacity can be costly. section 6.4.3
This is a general model, not a rule for every machine. Operating systems and CPUs differ in how they cooperate, and some constrained systems, such as microcontrollers, use real addressing instead. section 6.4.3
