A translation lookaside buffer, or TLB, is the CPU’s cache of recently translated memory addresses. Programs use virtual addresses, but accessing RAM requires physical addresses. The CPU’s memory management unit (MMU) performs the translation using mappings managed by the operating system. section 6.4.1 section 6.4.3
Without a cached translation, a memory access can require one lookup for the mapping and another for the requested data. Keeping recent translations in fast CPU memory helps avoid that worst case. Addresses are grouped into pages, typically 4 KB, so a mapping is not needed for every variable. section 6.4.3
Why data layout can matter
An x86 TLB might hold translations for around 100 pages. A program that reaches beyond that capacity can pay a performance cost. This is one reason to keep data structures lean and avoid deeply nested structures; the precise behavior depends on the CPU and operating system. section 6.4.3
