A non-maskable interrupt (NMI) is a processor interrupt that ordinary interrupt masking cannot disable. On the NES, the PPU generates an NMI when it finishes drawing a screen and enters vBlank. The 6502 stops its current work and begins the NMI routine whose address is stored in the vector table. section 1.5.4 section 5.13
vBlank is the short interval while the display raster returns to the top of the screen. It is the normal time to update PPU video memory, because changing VRAM while the PPU is drawing can produce incorrect output and takes longer. An NMI therefore provides a regular point for screen updates, music, and sound effects. section 1.5.4 section 5.13
A safe NMI routine follows a small sequence:
- Save A, X, and Y on the stack immediately, because the interrupt may arrive during code that still needs those register values. section 5.13
- Check a zero-page flag such as nmi_ready to decide whether rendering work should run, skip VRAM writes, or disable rendering for larger video-memory changes. section 5.13
- Perform scheduled PPU work, such as transferring the sprite table, copying palette data, and setting rendering state. section 5.13
- Restore Y, X, and A from the stack, then use rti to return to the interrupted code without corrupting its state. section 5.13
Frame-driven sprite and palette update
An NMI can begin by pushing A, X, and Y. If nmi_ready permits rendering, it sets the sprite-RAM address, starts a sprite DMA transfer, writes the 32-byte palette through the PPU VRAM registers, enables rendering, and clears nmi_ready. It then pulls Y, X, and A and returns with rti. section 5.13
Figure 1.6 NES PPU chip: What is a vBlank?
Use the vBlank diagram to see why the PPU pauses after reaching the bottom of the display and why the NMI aligns updates with that pause. section 1.5.4
