The PPU status register reports NES display and rendering state. During startup, read it with the 6502 BIT instruction to wait for the first vBlank before continuing. section 5.12
A vBlank wait uses the register’s bit 7:
- Read PPU_STATUS once to clear any previous “vBlank has happened” flag. section 5.12
- Use BIT PPU_STATUS so bit 7 controls the processor’s negative flag; the accumulator value does not matter. section 5.12
- Loop with BPL while bit 7 is clear, exiting when the PPU signals vBlank. section 5.12
Waiting for the first vBlank
bit PPU_STATUS wait_vblank: bit PPU_STATUS bpl wait_vblank The initial read clears a stale flag; the loop then waits for a complete rendered frame. section 5.12
Listing 5.13 Waiting for the first vBlank (example.s)
#1
bit PPU_STATUS
wait_vblank:
bit PPU_STATUS
bpl wait_vblank
View the complete assembly listing for the first-vBlank wait. section 5.12
