Write-back with invalidation is a cache-coherence protocol for shared variables on multiprocessor systems. When one processor updates a cached value, other caches holding the same memory block detect the update through bus messages. They either apply the update or invalidate their cache line; an invalidated line is refetched from main memory when needed. section 3.1
Two CPUs sharing a variable
Thread 2 may retain an outdated copy in its local CPU cache after thread 1 updates the value. Invalidation removes thread 2’s stale cache line, so its next read fetches the updated value from memory. section 3.1
Use the cache-update figure to trace how a shared-variable write reaches other caches. section 3.1
