A cache coherence protocol coordinates per-core caches so copies of shared data remain consistent. When one core writes cached data, other caches update or invalidate their copies instead of returning stale values. section 6.4
Coherence lets programs read and write memory as though no cache intervened, but coordination adds latency and makes updates more expensive. Distributed caches may instead tolerate stale reads. section 6.4
Two cores cache the same value
Two CPU cores read the same memory region and cache it locally. If one core writes the value, a coherence protocol ensures the other cache updates or invalidates its copy, preventing an incoherent view. section 6.4
MESI models each cache line, such as a 64-byte block, with states including:
- Modified (M): one cache holds a valid, modified copy and may change it further. section 6.4
- Exclusive (E): one cache holds an unmodified copy matching main memory. section 6.4
