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MESI

As explained in Latency

MESI is a cache coherence protocol whose cache-line states are Modified, Exclusive, Shared, and Invalid.

MESI is a cache coherence protocol that keeps multicore caches from returning stale data. Each cached line occupies one of four states: Modified, Exclusive, Shared, or Invalid. section 6.4

The states describe ownership, validity, and agreement with main memory:

  • Modified (M): one cache holds a valid copy changed from main memory and may modify it further. section 6.4
  • Exclusive (E): one cache holds an unmodified copy matching main memory; a write changes it to Modified. section 6.4
  • Shared (S): multiple caches may hold valid, unmodified copies matching main memory. section 6.4
  • Invalid (I): the cache line is absent or unusable. section 6.4

A read followed by a write

When a core reads an Invalid line, it obtains the data and receives Exclusive state if no other cache holds it, or Shared state otherwise. Writing a Shared line requires invalidating the other cached copies before the writer can obtain exclusive ownership. section 6.4

How Latency covers it

How deep it goes
Defines four cache-line states and describes read behavior plus invalidation required before writing shared data.
Examples
Uses multicore local caches, main-memory reads, and a 64-byte cache line to illustrate state ownership.
What it assumes
Assumes familiarity with CPU caches and memory, while defining cache coherence and each MESI state.
What you can do after
Evaluate how cached reads and writes preserve consistency across CPU cores.
How it connects
Connects cache coherence with CPU cores, local caches, cache lines, main memory, and invalidation.

Related concepts

This explainer was generated by Manning's knowledge graph from the text of Latency. The section links point to the parts of the book it draws on.