A CPU exception interrupts normal execution when the CPU encounters a problem while processing an instruction, such as an illegal instruction or an invalid memory address. It is also called a synchronous interrupt. Unlike a hardware interrupt from a device, it arises during the CPU’s own processing. section 12.1.1
Exception names describe whether execution can recover:
- A fault is recoverable. A page fault, for example, gives the operating system a chance to address a memory-access problem. section 12.1
- A trap is recoverable; CPU-detected integer overflow is one example. section 12.1
- An abort is unrecoverable and terminates the application. section 12.1
When an interrupt occurs, the CPU transfers control to handler code whose location was established during boot. An operating-system signal is different: it interrupts an application’s control flow, and many signals can be ignored. Treating signals as interrupts can be a useful learning model, but it does not make them the same thing. section 12.1.1 section 12.11
A minimal kernel handler
A small Rust kernel can declare an empty `eh_personality` function. During exception handling, a personality function is called as stack frames are unwound to determine whether a frame can handle the exception. An empty function handles none: the kernel still crashes when an error occurs. It is a starting framework, not recovery. section 11.4.1 section 11.4
Do not confuse this CPU meaning with every use of “error” in Rust. A fallible conversion can return `Result`, containing either a value or an error; calling `unwrap()` on a failure can crash the program. That is a programming-language error-handling example, not a definition of a CPU exception. section 2.3.3 section 12.1
Figure 12.1 A visual taxonomy of how the terms interrupt, exception, trap, and fault interact within Intel’s x86 family of CPUs. Note that signals do not appear within this figure. Signals are not interrupts.
Use the taxonomy figure to locate faults, traps, and aborts under exceptions and to keep signals outside the interrupt family. section 12.1
