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Cache line

As explained in Latency

A cache line is a fixed-size block of memory stored and managed as a unit in a CPU cache.

A cache line is a fixed-size memory block stored and managed as one unit in a CPU cache. In multicore systems, cache lines are the units whose copies must remain coherent across cores. section 6.4 section 6.4

MESI assigns each cache line a coherence state:

  • Modified (M): one cache holds a changed, valid copy. section 6.4
  • Exclusive (E): one cache holds an unchanged copy matching main memory. section 6.4
  • Shared (S): multiple caches hold unchanged copies matching main memory. section 6.4
  • Invalid (I): the cache line is absent or unusable. section 6.4

Read and write transitions

A read uses a local line in Modified, Exclusive, or Shared state. A miss fetches the line from main memory. Writing a Shared line requires invalidating other cached copies before obtaining an exclusive copy. section 6.4

How Latency covers it

How deep it goes
Defines a 64-byte example and details MESI states plus read and write transitions, without measuring performance or cache placement.
Examples
Uses a 64-byte cached block and follows local reads, memory misses, shared copies, and invalidation during writes.
What you can do after
Evaluate/understand cache-line states and coherence actions during multicore reads and writes.
How it connects
Connects cache lines with CPU caches, cache coherence, main memory, MESI, and MOSI.
Cover of Latency
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