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Cache line

As explained in Rust in Action: Systems programming concepts and techniques

A cache line is a small fixed-size block of data transferred between RAM and a processor cache as a unit.

A cache line is a small, fixed-size block of data transferred between RAM and a processor cache as one unit. section 6.4.3

Keep cache lines distinct from the translation lookaside buffer (TLB): the TLB caches recently translated addresses, while a cache line describes a data-transfer unit between RAM and processor cache. section 6.4.3

How Rust in Action: Systems programming concepts and techniques covers it

How deep it goes
Defines the transfer unit and distinguishes it from the TLB, but stops short of cache-line layout or performance internals.
What you can do after
Evaluate memory behavior by distinguishing cached data transfers from cached address translations.
How it connects
Connects processor caches with RAM, virtual addresses, physical addresses, and translation lookaside buffers.

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