Cache line

As explained in Learn Concurrent Programming with Go

A cache line is a block-sized unit of memory storage that a cache transfers and tracks as a copy of main memory.

A cache line is a block-sized unit of memory that a processor cache transfers and tracks as a copy of main memory. When one thread updates shared data, another processor may still hold an older copy of the same cache line. section 3.1

Shared-memory updates expose several cache-line behaviors:

• Write-through mirrors an updated cache value back to main memory, but another CPU cache may still retain an outdated copy. section 3.1
• Caches can listen for bus update messages and either apply the change or invalidate the affected cache line. section 3.1
• Invalidation forces a later read to fetch a fresh copy from memory, while increasingly many processors make coherence more complex and costly. section 3.1

Figure 3.4 Updating shared variables in an architecture with caches

Follow the figure to visualize shared-variable updates across processor caches. section 3.1

How Learn Concurrent Programming with Go covers it

How deep it goes

Traces cache copies, write-through, bus notifications, invalidation, and the scalability limit called the coherency wall.

Examples

Uses shared-variable updates, two processor caches, bus messages, and cache-line invalidation as visual examples.

What it assumes

Assumes familiarity with threads, shared variables, processor caches, and main memory.

What you can do after

Understand how invalidation helps processors obtain updated shared values and why coherence can constrain scaling.

How it connects

Connects cache lines with main memory, processor caches, memory sharing, and cache-coherency protocols.

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Also explained in

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  100 Go Mistakes and How to Avoid ThemA cache line is the fixed-size unit of contiguous memory transferred between main memory and a processor cache.
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  Rust in Action: Systems programming concepts and techniquesA cache line is a small fixed-size block of data transferred between RAM and a processor cache as a unit.
• 

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  LatencyA cache line is a fixed-size block of memory stored and managed as a unit in a CPU cache.

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Related concepts

• false sharingused by · False sharing is a performance problem in which independent data accessed by different threads occupy the same cache line, causing unnecessary cache-coherence traffic when that data is modified.
• CPU cachepart of · A CPU cache is small, fast memory that stores copies of data or instructions for quicker access by a processor.
• hardwareused by · Hardware is the physical equipment and components of a computing system that provide resources for computation and software execution.
• spatial localityused by · Spatial locality is the tendency for memory locations near a recently accessed location to be accessed soon afterward.

This explainer was generated by Manning's knowledge graph from the text of Learn Concurrent Programming with Go. The section links point to the parts of the book it draws on.