A cache-coherent system keeps multiple caches consistent when they hold data from the same memory region. In a multicore CPU, each core may cache the same data; when one core writes, other caches must update or invalidate their copies so programs do not read stale values. section 6.4
Two cores sharing a value
Suppose two cores cache the same memory value. Both can initially read their local copies, but a write by one core makes the other copy stale unless the caches coordinate. A coherence protocol such as MESI manages this coordination for cache lines, such as a 64-byte block. The consistency guarantee simplifies programming, but coordination adds latency to updates. section 6.4
Cache coherence is distinct from general distributed-cache freshness. Distributed caches may intentionally remain incoherent when applications can tolerate stale reads, avoiding the coordination cost of keeping every copy current. section 6.4 section 6.11
