Cache-coherent system

As explained in Learn Concurrent Programming with Go

Cache coherence is the coordination of cached copies so that processors observe consistent values for shared memory locations.

A cache-coherent system keeps processors from using conflicting cached copies of the same shared-memory location. When one processor writes an update, other caches listen for the bus message and either apply the update or invalidate the affected cache line. Invalidated data is fetched again from memory when needed, ensuring a later read can obtain the updated value. Write-back with invalidation is one cache-coherence protocol; modern architectures combine multiple protocols. Scaling this coordination across many cores can become costly, creating a potential coherency wall. section 3.1

An updated shared variable

Imagine thread 1 updates a shared variable while thread 2 retains an older copy in another CPU cache. A coherence mechanism broadcasts the memory update; thread 2’s cache either updates its copy or discards the cache line and reloads the value later. section 3.1

Figure 3.4 Updating shared variables in an architecture with caches

Trace how a shared-variable update moves through processor caches and memory. section 3.1

How Learn Concurrent Programming with Go covers it

How deep it goes

Explains cache updates, invalidation, write-back, and scaling limits without detailing complete modern protocols.

Examples

Uses two threads, bus update messages, stale cache copies, and a shared-variable update diagram.

What it assumes

Assumes shared-memory communication and processors with local caches, while defining cache coherence through a concrete stale-copy scenario.

What you can do after

Evaluate how processors obtain updated shared values when local cache copies become stale.

How it connects

Links shared memory, processor caches, main memory, cache lines, and cache-coherency protocols.

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Also explained in

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  liveBookmanning.com
  LatencyCache coherence is the property that multiple caches maintain mutually consistent views of shared data.

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Related concepts

• MESIaddressed by · MESI is a cache-coherence protocol that assigns each cache line one of four states: Modified, Exclusive, Shared, or Invalid.
• consistencycontrasts with · Consistency is the property of related data, behavior, outputs, or states agreeing with one another or conforming to defined rules across relevant instances or operations.
• cache coherence protocolimplemented by · A cache coherence protocol is a set of rules that coordinates caches so copies of shared data are updated or invalidated consistently.
• write-back with invalidationincludes · Write-back with invalidation is a cache-coherence protocol that propagates an updated cached value and invalidates stale copies in other caches.

This explainer was generated by Manning's knowledge graph from the text of Learn Concurrent Programming with Go. The section links point to the parts of the book it draws on.