liveBook · Manning

Throughput

As explained in Transformers in Action

Throughput is the amount of inference work completed per unit of time, such as generated tokens or served requests per second.

Throughput measures how much inference work is completed per unit of time, such as generated tokens or served requests per second. In large-language-model deployment, inference optimization raises throughput without changing the model architecture by improving operation scheduling, memory access, and GPU utilization. section 9.3

Autoregressive generation limits throughput because each token depends on earlier tokens. KV caching avoids recomputing the full attention context: previously calculated key and value vectors are stored and reused, while the query for the new token is recomputed. This reduces repeated work, although the cache consumes more memory as sequences and batch sizes grow. section 9.3

GPU memory behavior also determines achievable throughput. Tiling reuses data in fast shared memory, while coalesced access lets warp threads read contiguous addresses and reduces wasted memory transactions. Poor layouts, transpositions, or scattered accesses can instead make memory bandwidth the bottleneck. section 9.4

Measuring and improving inference throughput

A practical benchmark compares generation with and without KV caching for a Llama 3.2 3B Instruct model by recording inference durations. A deployment can then expose a Gemma 3 model through vLLM, while GPU-level improvements target memory layout, tiling, and thread access patterns. section 9.4

How Transformers in Action covers it

How deep it goes
Explains throughput through KV caching, memory growth, scheduling, layouts, tiling, and coalesced GPU access, but stops short of a throughput formula.
Examples
Demonstrates cache-enabled generation benchmarking, vLLM serving, tiled matrix multiplication, and row-major versus column-major layouts.
What it assumes
Assumes familiarity with autoregressive transformers, attention, tensors, and GPU execution while explaining KV caching and memory access patterns.
What you can do after
Diagnose throughput bottlenecks by comparing KV-cache behavior and examining GPU memory layout, bandwidth, tiling, and access coalescing.
How it connects
Connects throughput to inference optimization, latency, autoregressive transformers, KV caching, memory bandwidth, tiling, and coalesced memory access.

Also explained in

Compare how 20 books explain throughput →

Related concepts

This explainer was generated by Manning's knowledge graph from the text of Transformers in Action. The section links point to the parts of the book it draws on.